A flash memory device is a nonvolatile memory device that does not lose data stored therein even if power is turned off. In addition, the flash memory device can record, read, and delete data at a relatively high speed.
Flash memory devices are used as Bios of a personal computer (PC), a set-top box, a printer, and a network server in order to store data. Recently, flash memory devices have been used for digital cameras, portable phones, and other portable electronics.
In a flash memory device, a semiconductor device having a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure is typically used.
Unlike a flash memory device having a floating gate including polycrystalline silicon, a SONOS memory device is a charge-trap type device, in which gate voltage is applied to charges so that the charges pass through a thin oxide layer formed on silicon. The charges are injected into or released from a trap formed in a silicon nitride layer.
Electron injection schemes for a memory cell having a SONOS structure according to the related art can be classified into a Fowler-Nordheim (FN) tunneling scheme and a channel hot electron injection scheme. These two schemes each have advantages and disadvantages. The FN tunneling scheme has an advantage of low programming current, but a programming time on the order of a few milliseconds is required. In addition, a tunnel oxide layer must have a thickness of only 20 to 30 Å, so the FN tunneling scheme has a disadvantage in terms of retention. Further, a high gate bias is required, so a high voltage device, a driving circuit, and a pump circuit are necessary.
The channel hot electron injection scheme has an advantage of high speed programming on the order of a few microseconds, but high current of several hundreds of microamps is required for cell programming, so the channel hot electron injection scheme is not suitable for mobile products having high power consumption.
In addition, if a cell having a 1-Tr structure is used, over-erase may occur during the erase operation, so a recovery operation may be required. In order to avoid the over-erase, all cells must be controlled to have a uniform erase speed.
In a memory array according to the related art, high voltage is applied to a bit line, so an x-decoder used for selectively applying bias to a specific bit line must include a high voltage transistor that occupies a large area.
FIGS. 1A and 1B are cross-sectional views showing a procedure for manufacturing a flash memory device according to the related art.
Referring to FIG. 1A, when a split select gate is defined by a photo and etch process, select gate lengths of cells may be different from each other (L1≠L2) due to the overlay misalign in the photo process, so a left cell (A-Cell) may have different characteristics than a right cell (B-Cell).
Referring to FIG. 1B, when the split select gate is defined by the photo and etch process in a state in which a local nitride layer is used as a memory site, the cells may have various nitride lengths (L3≠L4) and select gate lengths (L1≠L2) due to the CD variation and overlay misalign in the photo process. Thus, characteristic variation of the left cell (A-Cell) and the right cell (B-Cell) can be increased.